1. Field of Invention
The present invention relates to a semiconductor device provided with memory cells for storing data and sense amplifiers for reading data from the memory cells.
2. Description of the Related Art
With the trend toward greater capacity in semiconductor memory devices such as DRAM (Dynamic RAM) in recent years, a wide variety of designs have been proposed for the layout of memory cell arrays that are provided with a plurality of memory cells and sense amplifiers for reading data from the memory cells, one of these designs being the open bit-line system. The configuration of the open bit-line system is described in, for example, Japanese Patent Laid-Open Publication No. 2001-102549 and Japanese Patent Laid-Open Publication No. 2001-273764. As shown in FIG. 1, the open bit-line system is a configuration provided with a plurality of sense amplifier columns 110 that are composed of a plurality of sense amplifiers arranged in a column, and a plurality of memory cell arrays (cell plates) 100; sense amplifier columns 110 and memory cell arrays 100 being alternately arranged. Each sense amplifier is connected to two adjacent memory cell arrays 100 by a pair of bit lines 120, and reproduce data that are stored by complementary signals (two signals of opposite phase) that are received from the memory cells by way of bit lines 120.
The alternate arrangement of memory cell arrays 100 and sense amplifier columns 110 in the open bit-line system means that the number of memory cells that can be accessed in the memory cell arrays (reference plates) that are arranged outermost is reduced by half. In other words, the open bit-line system, due to its necessity for reference plates, entails the disadvantage of reduced chip size.
One example for circumventing this problem adopts a configuration in which sense amplifier column 110a is formed by an arrangement that concentrates a plurality of sense amplifiers between two memory cell arrays (cell plate) 100a (hereinbelow referred to as “sense amplifier concentrated arrangement”) (See FIG. 2).
The sense amplifier concentrated arrangement does not require the above-described reference plate, and is advantageous from the standpoints of compact chip size and improved integration.
However, when laying out interconnections in the semiconductor device, the standard values for each interconnection width are found based on the level of integration and the necessary current-carrying capacity, and interconnection spacing is determined from these standard values. More specifically, where the standard value of the interconnection width is F, interconnections are each arranged to have an interconnection spacing having a pitch of at least 2 F, which is the minimum pitch.
Within a memory cell array, sufficient interconnect spacing must be ensured in order to avoid memory cells that are arranged in a matrix, and bit lines and word lines are arranged at a pitch of 3 F.
Within a sense amplifier in which memory cells do not exist, however, each interconnect is arranged at a pitch of 2 F in order to reduce the layout area. Interconnect spacing is therefore narrower within a sense amplifier than within a memory cell array, and there is the consequent concern for an increase in the influence of noise produced by coupling between signals.
For the purpose of achieving higher-speed data reproduction by sense amplifiers in semiconductor devices of recent years, transfer gates are inserted between bit lines and sense amplifiers, and a process is carried out to isolate the sense amplifiers from bit lines having large capacitive load by turning OFF the transfer gates when amplifying bit line voltage inside a sense amplifier.
Although high-speed operation is possible in such a configuration because the capacitive load of bit lines on the sense amplifier side from the transfer gates (hereinbelow referred to as the “sense-amplifier-interior bit lines”) is reduced, noise tends to intrude from the outside, and this raises the danger that sufficient noise margin cannot be ensured in the sense amplifier.
No method has been proposed in the prior art for reducing this intrusion of noise in bit lines inside the sense amplifiers, and reducing noise has therefore been problematic.